// Copyright 2011 INDILINX Co., Ltd.
//
// This file is part of Jasmine.
//
// Jasmine is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Jasmine is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Jasmine. See the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.


#ifndef SDRAM_H
#define SDRAM_H

#define SDRAM_PARAM_SIGNATURE	0x4E36EDA5

typedef struct
{
	UINT32	init;
	UINT32	refresh;
	UINT32	timing;
	UINT32	mrs;
	UINT32	bytes;
} sdram_t;

#if PLL_CLK_CONFIG == PLL_133MHZ
	#define RDCLK_DLY	(2 << 0)
	#define SDCLK_DLY	(13 << 5)
#elif PLL_CLK_CONFIG == PLL_150MHZ
	#define RDCLK_DLY	(1 << 0)
	#define SDCLK_DLY	(10 << 5)
#elif PLL_CLK_CONFIG == PLL_155MHZ
	#define RDCLK_DLY	(1 << 0)
	#define SDCLK_DLY	(10 << 5)
#elif PLL_CLK_CONFIG == PLL_160MHZ
	#define RDCLK_DLY	(1 << 0)
	#define SDCLK_DLY	(9 << 5)
#elif PLL_CLK_CONFIG == PLL_165MHZ
	#define RDCLK_DLY	(2 << 0)
	#define SDCLK_DLY	(9 << 5)
#elif PLL_CLK_CONFIG == PLL_175MHZ || PLL_CLK_CONFIG == PLL_170MHZ
	#define RDCLK_DLY	(1 << 0)
	#define SDCLK_DLY	(7 << 5)
#elif PLL_CLK_CONFIG == PLL_180MHZ
	#define RDCLK_DLY	(1 << 0)
	#define SDCLK_DLY	(7 << 5)
#endif

// 50MHz, 16MB
#define SDRAM_PARAM_50_16_INIT			(SDRAM_16MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_50_16_REFRESH		(SDRAM_RF_PERIOD(400) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_50_16_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_50_16_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 50MHz, 32MB
#define SDRAM_PARAM_50_32_INIT			(SDRAM_32MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_50_32_REFRESH		(SDRAM_RF_PERIOD(400) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_50_32_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_50_32_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 50MHz, 64MB
#define SDRAM_PARAM_50_64_INIT			(SDRAM_64MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_50_64_REFRESH		(SDRAM_RF_PERIOD(400) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_50_64_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_50_64_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 60MHz, 16MB
#define SDRAM_PARAM_60_16_INIT			(SDRAM_16MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_60_16_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_60_16_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_60_16_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 60MHz, 32MB
#define SDRAM_PARAM_60_32_INIT			(SDRAM_32MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_60_32_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_60_32_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_60_32_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 60MHz, 64MB
#define SDRAM_PARAM_60_64_INIT			(SDRAM_64MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_60_64_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_60_64_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_60_64_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 60MHz, safe value
#define SDRAM_PARAM_60_SAFE_INIT		(SDRAM_64MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_60_SAFE_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_60_SAFE_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_60_SAFE_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 75MHz, 16MB		// not verified
#define SDRAM_PARAM_75_16_INIT			(SDRAM_16MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_75_16_REFRESH       (SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_75_16_TIMING        (SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_75_16_MRS           (SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 75MHz, 32MB		// not verified
#define SDRAM_PARAM_75_32_INIT          (SDRAM_32MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_75_32_REFRESH       (SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_75_32_TIMING        (SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_75_32_MRS           (SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 75MHz, 64MB
#define SDRAM_PARAM_75_64_INIT			(SDRAM_64MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_75_64_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_75_64_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_75_64_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 75MHz, safe value
#define SDRAM_PARAM_75_SAFE_INIT		(SDRAM_64MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_75_SAFE_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_75_SAFE_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_75_SAFE_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 100MHz, 64MB
#define SDRAM_PARAM_100_64_INIT			(SDRAM_64MB | SDRAM_CL_2 | SDRAM_RAS(1) | SDRAM_INIT_PERIOD(0x00002EE0))
#define SDRAM_PARAM_100_64_REFRESH		(SDRAM_RF_PERIOD(516) | SDRAM_TRC(4) | SDRAM_TRP(2))
#define SDRAM_PARAM_100_64_TIMING		(SDRAM_RDCLK_DLY(8) | SDRAM_RD_CAP_DLY_0(1) | SDRAM_SDCLK_DLY(8) | SDRAM_RD_CAP_DLY_1(0) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_100_64_MRS			(SDRAM_MRS_KEY(0x027) | SDRAM_EMRS_KEY(0x000))

// 133MHz, 16MB
#define SDRAM_PARAM_133_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_133_16_REFRESH		(SDRAM_RF_PERIOD(2076) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_133_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_133_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 133MHz, 32MB
#define SDRAM_PARAM_133_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_133_32_REFRESH		(SDRAM_RF_PERIOD(2076) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_133_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_133_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 133MHz, 64MB
#define SDRAM_PARAM_133_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_133_64_REFRESH		(SDRAM_RF_PERIOD(1038) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_133_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_133_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 150MHz, 16MB
#define SDRAM_PARAM_150_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(40000))
#define SDRAM_PARAM_150_16_REFRESH		(SDRAM_RF_PERIOD(2340) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_150_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_150_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 150MHz, 32MB
#define SDRAM_PARAM_150_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(40000))
#define SDRAM_PARAM_150_32_REFRESH		(SDRAM_RF_PERIOD(2340) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_150_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_150_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 150MHz, 64MB
#define SDRAM_PARAM_150_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(40000))
#define SDRAM_PARAM_150_64_REFRESH		(SDRAM_RF_PERIOD(1288) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_150_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_150_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 155MHz, 16MB
#define SDRAM_PARAM_155_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_155_16_REFRESH		(SDRAM_RF_PERIOD(1100) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_155_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_155_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 155MHz, 32MB
#define SDRAM_PARAM_155_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_155_32_REFRESH		(SDRAM_RF_PERIOD(1100) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_155_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_155_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 155MHz, 64MB
#define SDRAM_PARAM_155_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_155_64_REFRESH		(SDRAM_RF_PERIOD(1100) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_155_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_155_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 160MHz, 16MB
#define SDRAM_PARAM_160_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_160_16_REFRESH		(SDRAM_RF_PERIOD(1249) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_160_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_160_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 160MHz, 32MB
#define SDRAM_PARAM_160_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_160_32_REFRESH		(SDRAM_RF_PERIOD(1249) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_160_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_160_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 160MHz, 64MB
#define SDRAM_PARAM_160_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(33536))
#define SDRAM_PARAM_160_64_REFRESH		(SDRAM_RF_PERIOD(1249) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_160_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_160_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 165MHz, 16MB
#define SDRAM_PARAM_165_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(37000))
#define SDRAM_PARAM_165_16_REFRESH		(SDRAM_RF_PERIOD(2570) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_165_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_165_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 165MHz, 32MB
#define SDRAM_PARAM_165_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(37000))
#define SDRAM_PARAM_165_32_REFRESH		(SDRAM_RF_PERIOD(2570) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_165_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_165_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 165MHz, 64MB
#define SDRAM_PARAM_165_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(37000))
#define SDRAM_PARAM_165_64_REFRESH		(SDRAM_RF_PERIOD(1280) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_165_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_165_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 170MHz, 64MB
#define SDRAM_PARAM_170_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(36500))
#define SDRAM_PARAM_170_64_REFRESH		(SDRAM_RF_PERIOD(1284) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_170_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_170_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 175MHz, 16MB
#define SDRAM_PARAM_175_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(37000))
#define SDRAM_PARAM_175_16_REFRESH		(SDRAM_RF_PERIOD(2570) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_175_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_175_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))
// 175MHz, 32MB
#define SDRAM_PARAM_175_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(37000))
#define SDRAM_PARAM_175_32_REFRESH		(SDRAM_RF_PERIOD(2570) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_175_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_175_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 175MHz, 64MB
#define SDRAM_PARAM_175_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(36000))
#define SDRAM_PARAM_175_64_REFRESH		(SDRAM_RF_PERIOD(1288) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_175_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_175_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 180MHz, 16MB		// not verified
#define SDRAM_PARAM_180_16_INIT			(SDRAM_16MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(36000))
#define SDRAM_PARAM_180_16_REFRESH		(SDRAM_RF_PERIOD(1288) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_180_16_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_180_16_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 180MHz, 32MB
#define SDRAM_PARAM_180_32_INIT			(SDRAM_32MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(36000))
#define SDRAM_PARAM_180_32_REFRESH		(SDRAM_RF_PERIOD(1288) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_180_32_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_180_32_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

// 180MHz, 64MB		// not verified
#define SDRAM_PARAM_180_64_INIT			(SDRAM_64MB | SDRAM_CL_3 | SDRAM_RAS(5) | SDRAM_INIT_PERIOD(36000))
#define SDRAM_PARAM_180_64_REFRESH		(SDRAM_RF_PERIOD(1288) | SDRAM_TRC(14) | SDRAM_TRP(3))
#define SDRAM_PARAM_180_64_TIMING		(RDCLK_DLY | SDRAM_RD_CAP_DLY_0(1) | SDCLK_DLY | SDRAM_RD_CAP_DLY_1(1) | SDRAM_CAP_CLK_SEL(1))
#define SDRAM_PARAM_180_64_MRS			(SDRAM_MRS_KEY(0x037) | SDRAM_EMRS_KEY(0x000))

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_50MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_50_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_50_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_50_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_50_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_60MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_60_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_60_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_60_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_60_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_60MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_60_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_60_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_60_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_60_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_60MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_60_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_60_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_60_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_60_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_75MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_75_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_75_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_75_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_75_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_75MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_75_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_75_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_75_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_75_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_75MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_75_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_75_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_75_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_75_64_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_100MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_100_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_100_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_100_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_100_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_133MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_133_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_133_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_133_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_133_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_133MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_133_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_133_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_133_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_133_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_133MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_133_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_133_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_133_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_133_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_150MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_150_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_150_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_150_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_150_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_150MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_150_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_150_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_150_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_150_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_150MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_150_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_150_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_150_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_150_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_155MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_155_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_155_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_155_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_155_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_155MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_155_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_155_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_155_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_155_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_155MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_155_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_155_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_155_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_155_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_160MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_160_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_160_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_160_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_160_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_160MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_160_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_160_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_160_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_160_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_160MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_160_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_160_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_160_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_160_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_165MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_165_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_165_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_165_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_165_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_165MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_165_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_165_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_165_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_165_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_165MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_165_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_165_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_165_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_165_64_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_170MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_170_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_170_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_170_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_170_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_175MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_175_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_175_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_175_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_175_16_MRS
#endif
#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_175MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_175_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_175_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_175_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_175_32_MRS
#endif


#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_175MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_175_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_175_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_175_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_175_64_MRS
#endif

#if DRAM_SIZE == 16268800 && PLL_CLK_CONFIG == PLL_180MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_180_16_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_180_16_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_180_16_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_180_16_MRS
#endif

#if DRAM_SIZE == 32537600 && PLL_CLK_CONFIG == PLL_180MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_180_32_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_180_32_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_180_32_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_180_32_MRS
#endif

#if DRAM_SIZE == 65075200 && PLL_CLK_CONFIG == PLL_180MHZ
#define SDRAM_PARAM_MAIN_FW_INIT		SDRAM_PARAM_180_64_INIT
#define SDRAM_PARAM_MAIN_FW_REFRESH		SDRAM_PARAM_180_64_REFRESH
#define SDRAM_PARAM_MAIN_FW_TIMING		SDRAM_PARAM_180_64_TIMING
#define SDRAM_PARAM_MAIN_FW_MRS			SDRAM_PARAM_180_64_MRS
#endif

#if DRAM_SIZE == 16268800
#define SDRAM_PARAM_ROM_CODE_INIT		SDRAM_PARAM_75_16_INIT
#define SDRAM_PARAM_ROM_CODE_REFRESH	SDRAM_PARAM_75_16_REFRESH
#define SDRAM_PARAM_ROM_CODE_TIMING		SDRAM_PARAM_75_16_TIMING
#define SDRAM_PARAM_ROM_CODE_MRS		SDRAM_PARAM_75_16_MRS
#endif

#if DRAM_SIZE == 32537600
#define SDRAM_PARAM_ROM_CODE_INIT		SDRAM_PARAM_75_32_INIT
#define SDRAM_PARAM_ROM_CODE_REFRESH	SDRAM_PARAM_75_32_REFRESH
#define SDRAM_PARAM_ROM_CODE_TIMING		SDRAM_PARAM_75_32_TIMING
#define SDRAM_PARAM_ROM_CODE_MRS		SDRAM_PARAM_75_32_MRS
#endif

#if DRAM_SIZE == 65075200
#define SDRAM_PARAM_ROM_CODE_INIT		SDRAM_PARAM_75_64_INIT
#define SDRAM_PARAM_ROM_CODE_REFRESH	SDRAM_PARAM_75_64_REFRESH
#define SDRAM_PARAM_ROM_CODE_TIMING		SDRAM_PARAM_75_64_TIMING
#define SDRAM_PARAM_ROM_CODE_MRS		SDRAM_PARAM_75_64_MRS
#endif

#endif	// SDRAM_H

